CSIS Seminar

Memristive Nanoelectronics in Neuromorphic Computing and Considerations for Hardware Security

Abstract

Although CMOS technology scaling has been remarkable, it is also true that a significant slow-down in such scaling has occurred in recent years. This slower pace of technology advancement also means that modern computer systems can no longer rely exclusively on scaling for performance enhancements. Now is the time for circuit and system designers to consider alternative approaches to computer system architectures. One such approach is neuromorphic computing which uses models for biological neural systems to construct brain-inspired computer systems. Two basic components are required for a typical neuromorphic system: neurons that fire based on spike patterns received and synapses that provide weighted connections between neurons. Here we consider spiking neuromorphic systems where neurons are implemented using analog/mixed-signal CMOS and synapses are built from memristors (e.g. ReRAM). The specific neuromorphic framework presented also allows for recurrent pathways in the networks constructed, a feature that is particularly useful for stateful neuromorphic processing at the edge. We urther consider emerging memristive technology and novel computer architectures, such as neuromorphic, through the lens of hardware security. Specifically, memristor-based hardware security primitives are discussed in the context of lightweight security applications for embedded systems. While the emphasis is on what we can do with memristive nanoelectronics from a circuits and systems design perspective, early implementations of fabricated hybrid CMOS/memristive chips will also be presented and discussed. Note for people joining in-person only: Participants must complete Mason COVID Health✓™ and receive a “green light” status on the day of the event. Please send your RSVP request to ece@gmu.edu with the info of seminar date, seminar title, your name. Zoom link: https://gmu.zoom.us/j/94920236381

Speaker Bio

Garrett S. Rose received the B.S. degree in computer engineering from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, in 2001 and the M.S. and Ph.D. degrees in electrical engineering from the University of Virginia, Charlottesville, in 2003 and 2006, respectively. His Ph.D. dissertation was on the topic of circuit design methodologies for molecular electronic circuits and computing architectures. Presently, he is a Professor in the Min H. Kao Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville where his work is focused on research in the areas of nanoelectronic circuit design, neuromorphic computing and hardware security. Prior to that, from June 2011 to July 2014, he was with the Air Force Research Laboratory, Information Directorate, Rome, NY. From August 2006 to May 2011, he was an Assistant Professor in the Department of Electrical and Computer Engineering at the Polytechnic Institute of New York University, Brooklyn, NY. From May 2004 to August 2005 he was with the MITRE Corporation, McLean, VA, involved in the design and simulation of nanoscale circuits and systems. His research interests include low-power circuits, system-on-chip design, trusted hardware, and developing VLSI design methodologies for novel nanoelectronic technologies.